VERILOG HDL

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1 Verilog digitalni dizajn Modelovanje, predstavljanje, simulacija digitalnog hardvera Konkurentno izvršavanje Paralelni tok podataka signali i vreme Specijalne jezičke konsrtrukcije Prelazi na okidnu ivicu kašnjenja Provera tajminga 1

2 Moduli Definicija primer module module_name ( port_list ); port declarations; variable declaration; description of behavior endmodule module HalfAdder (A, B, Sum Carry); input A, B; output Sum, Carry; assign Sum = A ^ B; //^ znači XOR assign Carry = A & B; // & znači AND endmodule 2

3 Načini opisa Strukturni: Verilog gate primitive Primer multiplekser: not n1(sel_n, sel); and a1(sel_b, b, sel_b); and a2(sel_a, a, sel); or o1(out, sel_b, sel_a); sel n1 b sel_n a a1 sel_b o1 out a2 sel_a 3

4 Načini opisa Dataflow: specificiraju se izlazni signali u funkciji ulaznih primer: assign out = (sel & a) (~sel & b); b sel sel_n sel_b out sel_a a 4

5 Behavioral: algoritamski Načini opisa Example: if (select == 0) begin out = b; end else if (select == 1) begin end out = a; a b Black Box 2x1 MUX out sel 5

6 Načini opisa Switch lewel: elektronicarski, nema u VHDLu module mynot (input x, output f); // internal declaration supply1 vdd; supply0 gnd; // NOT gate body pmos p1 (f, vdd, x); nmos n1 (f, gnd, x); endmodule 6

7 Leksičke konvencije Comentari: sintaksa iz jezika C // Single line comment /* Another single line comment */ /* Begins multi-line (block) comment All text within is ignored Line below ends multi-line comment */ Brojevi decimalni, hex, oktalni, binarni unsized decimalni size base forma String " između navodnika" 7

8 Leksičke konvencije Identifikatori A... Z a... z Underscore Stringovi limitirani na 1024 karaktera Prvi karakter nemože biti cifra 8

9 Ključne reči 9

10 Tipovi podataka net (wire, wand, wor, tri, triand, trior, trireg) reg vektor ceo broj realan broj niz (array) (nije string!) memorija parametar Oznaka Logičko stanje 0 logička nula 1 logička jedinica x nepoznato (neodređeno stanje) z stanje velike impedanse 10

11 Tpovi podataka Net Tipovi: fizicka veza između strukturnih elemenata Register Tip: apstraktni memorijski element Default vrednosti Net Types : z Register Type : x Net Tipovi: wire, tri, wor, trior, wand, triand, supply0, supply1 Register tipovi : reg, integer, time, real, realtime 11

12 Tipovi podataka Net Type: Wire wire [ msb : lsb ] wire1, wire2, Example wire Reset; // A 1-bit wire wire [6:0] Clear; // A 7-bit wire Register Type: Reg reg [ msb : lsb ] reg1, reg2, Example reg [ 3: 0 ] cla; // A 4-bit register reg cla; // A 1-bit register 12

13 Restrikcije Data Flow and Structural Modeling Can use only wire data type Cannot use reg data type Behavioral Modeling Can use only reg data type (within initial and always constructs) Cannot use wire data type 13

14 Memories An array of registers reg [ msb : lsb ] memory1 [ upper : lower ]; Example reg [ 0 : 3 ] mem [ 0 : 63 ]; // An array of 64 4-bit registers reg mem [ 0 : 4 ]; // An array of 5 1-bit registers 14

15 Operatori Podela: unarni, binarni, ternarni operatori. Primeri: a = ~b; // ~ je unarni operator. b je operand. a = b && c; // && je binarni operator. b i c su // operandi. a = b? c : d; //?: je ternarni operator. b, c i d su // operandi. 15

16 Operatori Tipovi: dele se na Aritmetičke (+ * / %) logičke (&&!) Relacione (> < >= <= ) jednakosti ( ==!= ===!==) Bitwise ( ~ & ^ ~^) Redukcione ( & ~ & ~ ^ ~^) polazi se od MSB Pomeračke (>> <<) pridruživanja (primer) Umnožavanja (primer) Uslovni (primer) 16

17 Spaja više operanada (mogu biti vektori i skalari). Dužina vektorskih operanada treba da je unapred definisana. I delovi vektora mogu biti operandi. Pridruživanje 17

18 Prvi operand konstanta određuje koliko puta treba napisati drugi operand jedan iza drugog.. Umno.avanje se mo.e kombinovati sa pridru.ivanjem. Umnožavanje 18

19 ? USLOVNA OPERACIJA Ako je uslov neodređen (x) rezultantni vektor se sastoji iz poklapajućih bitova operanada i x-ova na mestima gde se ne poklapaju vrednosti. Radi kao multiplekser 2/1 ali može da se koristi i kao kolo za sprezanje sa tri stanja. // Opisivanje multipleksera 2/1 assign out = control? in1 : in2; // Modeliranje kola za sprezanje sa tri stanja assign addr_bus = drive_enable? addr_out : 32 bz; // Rekurzivno korišćenje uslovne operacije. reg [1:0] A, B; // Podaci A, B su reg tipa, veličine 2 bita. assign out = A[0]? ( B[0]? 1 b1 : 1 b0 ) : ( B[0]? 1 b0 : 1 b1); 19

20 Prioritet operatora Operator i simbol Unary, Multiply, Divide, Modulus!, ~, *, /, % Add, Subtract, Shift +, -, <<, >> Relation, Equality <,>,<=,>=,==,!=,===,!== Reduction &,!&,^,^~,,~ Logic &&, Conditional? : 20

21 Verilog gate primitive The gates have one scalar output and multiple scalar inputs. The 1st terminal in the list of gate terminals is an output and the other terminals are inputs. Gate Description And N-input AND gate Nand N-input NAND gate Or N-input OR gate Nor N-input NOR gate Xor N-input XOR gate Xnor N-input XNOR gate Za sintezu konsultovati alat koji se koristi! 21

22 Verilog gate primitive Gate Description Not N-output inverter Buf N-output buffer. Bufif0 Tristate buffer, Active low en. Bufif1 Tristate buffer, Active high en. Notif0 Tristate inverter, Low en. Notif1 Tristate inverter, High en. Tristate gates have three ports: the first is an output port, the second is a data port, and the third is a control port. The control port is used to set gates in high-impedance state. 22

23 Logic Value Description 0 zero, low, false 1 one, high, true z or Z high impedance, floating Logička stanja i fan-out x or X unknown, uninitialized, contention Verilog Strength Levels Strength Level 7 Supply Drive 6 Strong Pull 5 Pull Drive 4 Large Capacitance 3 Weak Drive 2 Medium Capacitance 1 Small Capacitance 0 Hi Impedance Specification Keyword supply0 supply1 strong0 strong1 pull0 pull1 large weak0 weak1 medium small highz0 highz1 23

24 Transmisioni gejtovi Transmission gates are bi-directional and can be resistive or non-resistive. Resistive devices reduce the signal strength which appears on the output by one level. All the switches only pass signals from source to drain, incorrect wiring of the devices will result in high impedance outputs. ASIC digital design Retko za FPGA sintezu Verolog AMS nije sinteza Nije analogna simulacija 24

25 Prekidači i transmisioni gejtovi There are six different switch primitives (transistor models) used in Verilog, nmos, pmos and cmos and the corresponding three resistive versions rnmos, rpmos and rcmos. The cmos type of switches have two gates and so have two control signals. Syntax: keyword unique_name (drain. source, gate) Gate Description 1. pmos Uni-directional PMOS switch 1. rpmos Resistive PMOS switch 2. nmos Uni-directional NMOS switch 2. rnmos Resistive NMOS switch 3. cmos Uni-directional CMOS switch 3. rcmos Resistive CMOS switch 4. tranif1 Bi-directional transistor (High) 4. tranif0 Bi-directional transistor (Low) 5. rtranif1 Resistive Transistor (High) 5. rtranif0 Resistive Transistor (Low) 6. tran Bi-directional pass transistor 6. rtran Resistive pass transistor 7. pullup Pull up resistor 8. pulldown Pull down resistor 25

26 Prekidači:nmos, pmos, rnmos, rpmos, cmos, rcmos The instantiation of these MOS switches can contain zero, one, two, or three delays The strength declaration is illegal. The nmos, pmos and cmos switches reduce supply strength of the signals to strong strength. Signals with others strengths are passed from input to output without a strength reduction. The rnmos, rpmos and rcmos switches reduce supply and strong strength of signals to pull strength. Thepull strength of signals is reduced to weak. The large and weak strength of signals are reduced to medium. The medium strength of signals is reduced to small. Signals with other strengths are passed from input to output without strength reduction. 26

27 rtranif0, rtranif1, tranif0 and tranif1 The instantiation of these bi-directional pass switches can contain zero, one, two, or three delays. The strength declaration is illegal. The tranif0 and tranif1 switches reduce supply strength of signals to strong. Signals with others strengths are passed from input to output without strength reduction. The rtranif0 andrtranif1 switches reduce supply and strong strength of signals to pull. The pull strength of signals is reduced to weak. The large and weak strength of signals are reduced to medium. The medium strength of signals is reduced to small. Signals with other strengths are passed from input to output without strength reduction. 27

28 tran and rtran The instance of these bidirectional switches cannot contain delay and strength declaration. The tran switches reduce supply strength of signals to strong strength. Signals with others strengths are passed from input to output without strength reduction. The rtran switches reduce supply and strong strength of signals to pull. The pull strength of signals is reduced to weak. The large and weak strength of signals are reduced to medium. The medium strength of signals is reduced to small. Signals with other strengths are passed from input to output without strength reduction. 28

29 pullup and pulldown The instantiation pullup and pulldown sources cannot contain delay declaration. The pullup can contain only strength1 specification (the strength0 declaration is optional). The pulldown can contain only strength0specification (the strength1 declaration is optional). The pullup source places a logic value 1 on connected signals. The pull down source places a logic value 0 on connected signals. 29

30 Na osnovu otpornosti veze Slabljenje intenziteta signala 30

31 Smanjenje intenziteta signala 31

32 Switch level dizajn, NAND module my_nand (input x, y, output f); supply1 vdd; supply0 gnd; wire a; // NAND gate body pmos p1 (f, vdd, x); pmos p2 (f, vdd, y); nmos n1 (f, a, x); nmos n2 (a, gnd, y); endmodule 32

33 Pseudo nmos NOR module pseudo_nor(input x, y, output f); supply0 gnd; // Pseudo nmos gate body nmos nx (f, gnd, x); nmos ny (f, gnd, y); pullup (f); endmodule 33

34 CMOS prekidač, digitalni! cmos [instance_name] (output, input, ncontrol, control); 34

35 2/1 Multiplexer 35

36 Bidirekcioni prekidači 36

37 Kašnjenja MOS/CMOS prekidača 37

38 Kašnjenja bidirekcionih prekidača 38

39 trireg Nets, states: Driven, Capacitive 39

40 trireg Nets, states: Driven, Capacitive 40

41 Strukturno modelovanje ponovo Izvršenje: konkurentno (paralelno) Format (Primitive Gates, ugrađeni) slično kao VHDL and G2(Carry, A, B); prvi parametar (Carry) Output Ostali prametri (A, B) Inputs Ožičena logika kašnjenja 41

42 Ožičena logika 42

43 Kašnjenja 43

44 Kašnjenja 44

45 kašnjenja 45

46 Gate Delay Specifications 46

47 Hazardi 47

48 A Static Hazard Example 48

49 A Dynamic Hazard Example 49

50 primer 50

51 MININIMALNE, TIPIČNE I MAKSIMALNE VREDNOSTI KAŠNJENJA - PRIMERI 51

52 Dataflow Modelovanje Continuous assignment statement Format: assign [ delay ] net = expression; Example: assign sum = a ^ b; Na ovaj način dajemo vrednost nosiocima podataka tipa net. Sa leve strane može i reg Delay: Time duration between assignment from RHS to LHS All continuous assignment statements execute concurrently Order of the statement does not impact the design Implicitni assign 52

53 Dataflow Modelovanje Kašnjenje primer: assign #2 sum = a ^ b; #2 znači 2 time-units Ako se ne specificira : 0 (podrazumevano) Associate time-unit with physical time `timescale time-unit/time-precision Example: `timescale 1ns/100 ps Timescale `timescale 1ns/100ps 1 Time unit = 1 ns Time precision is 100ps (0.1 ns) ns is interpreted as 10.5ns 53

54 Dataflow Modeling (cont.) Example: `timescale 1ns/100ps module HalfAdder (A, B, Sum, Carry); input A, B; output Sum, Carry; assign #3 Sum = A ^ B; assign #6 Carry = A & B; endmodule 54

55 Dataflow Modeling (cont.) 55

56 KAŠNJENJA U IMPLICITNIM DODELAMA 56

57 ZADAVANJE KAŠNJENJA PRI DEKLARISANJU NOSIOCA PODATKA TIPA net 57

58 Behavioral Modeling-OPIS NA NIVOU PONAŠANJA 58

59 Behavioral Modeling Example: module mux_2x1(a, b, sel, out); input a, a, sel; output out; or b or sel) begin if (sel == 1) out = a; else out = b; end endmodule Sensitivity List 59

60 Behavioral Modeling-OPIS NA NIVOU PONAŠANJA 60

61 Procedural Constructs Two Procedural Constructs initial Statement always Statement initial Statement : Executes only once always Statement : Executes in a loop Example: initial begin Sum = 0; Carry = 0; end or B) begin Sum = A ^ B; Carry = A & B; end 61

62 PROCEDURA TIPA initial 62

63 PROCEDURA TIPA initial -PRIMER 63

64 PROCEDURA TIPA always 64

65 Behavioral Modeling (cont.) always statement : Sequential Block Sequential Block: All statements within the block are executed sequentially When is it executed? Occurrence of an event in the sensitivity list Event: Change in the logical value Statements with a Sequential Block: Procedural Assignments Delay in Procedural Assignments Inter-Statement Delay Intra-Statement Delay 65

66 Behavioral Modeling (cont.) Inter-Assignment Delay Example: Sum = A ^ B; #2 Carry = A & B; Delayed execution Intra-Assignment Delay Example: Sum = A ^ B; Carry = #2 A & B; Delayed assignment 66

67 DODELE U initial I always PROCEDURAMA 67

68 BLOKIRAJUĆE DODELE 68

69 BLOKIRAJUĆE DODELE 69

70 Event Control Event Control Edge Triggered Event Control Level Triggered Event Control Edge Triggered Event (posedge CLK) //Positive Edge of CLK Curr_State = Next_state; Level Triggered Event (A or B) //change in values of A or B Out = A & B; 70

71 Loop Statements Loop Statements Repeat While For Repeat Loop Example: repeat (Count) sum = sum + 5; If condition is a x or z it is treated as 0 71

72 Loop Statements (cont.) While Loop Example: while (Count < 10) begin sum = sum + 5; Count = Count +1; end If condition is a x or z it is treated as 0 For Loop Example: for (Count = 0; Count < 10; Count = Count + 1) begin sum = sum + 5; end 72

73 Conditional Statements if Statement Format: if (condition) procedural_statement else if (condition) procedural_statement else procedural_statement Example: if (Clk) Q = 0; else Q = D; 73

74 Conditional Statements (cont.) Case Statement Example 1: case (X) 2 b00: Y = A + B; 2 b01: Y = A B; 2 b10: Y = A / B; endcase Example 2: case (3 b101 << 2) 3 b100: A = B + C; 4 b0100: A = B C; 5 b10100: A = B / C; //This statement is executed endcase 74

75 Conditional Statements (cont.) Variants of case Statements: casex and casez casez z is considered as a don t care casex both x and z are considered as don t cares Example: casez (X) 2 b1z: A = B + C; 2 b11: A = B / C; endcase 75

76 Compiler Directives `define (Similar to #define in C) used to define global parameter Example: `define BUS_WIDTH 16 reg [ `BUS_WIDTH - 1 : 0 ] System_Bus; `undef Removes the previously defined directive Example: `define BUS_WIDTH 16 reg [ `BUS_WIDTH - 1 : 0 ] System_Bus; `undef BUS_WIDTH 76

77 Compiler Directives (cont.) `include used to include another file Example `include./fulladder.v 77

78 Display tasks System Tasks $display : Displays the entire list at the time when statement is encountered $monitor : Whenever there is a change in any argument, displays the entire list at end of time step Simulation Control Task $finish : makes the simulator to exit $stop : suspends the simulation Time $time: gives the simulation 78

79 Type of Port Connections Connection by Position parent_mod 79

80 Type of Port Connections (cont.) Connection by Name parent_mod 80

81 Empty Port Connections If an input port of an instantiated module is empty, the port is set to a value of z (high impedance). module child_mod(in1, In2, Out1, Out2) input In1; input In2; output Out1; output Out2; module parent_mod(.) child_mod mod(a,,y1, Y2); //Empty Input endmodule //behavior relating In1 and In2 to Out1 endmodule If an output port of an instantiated module is left empty, the port is considered to be unused. module parent_mod(.) child_mod mod(a, B, Y1, ); //Empty Output endmodule 81

82 Test Bench `timescale 1ns/100ps module Top; reg PA, PB; wire PSum, PCarry; HalfAdder G1(PA, PB, PSum, PCarry); initial begin: LABEL reg [2:0] i; for (i=0; i<4; i=i+1) begin {PA, PB} = i; #5 $display ( PA=%b PB=%b PSum=%b PCarry=%b, PA, PB, PSum, PCarry); end // for end // initial endmodule Test Bench Apply Inputs Design Module Observe Outputs 82

83 Test Bench - Generating Stimulus Example: A sequence of values initial begin Clock = 0; #50 Clock = 1; #30 Clock = 0; #20 Clock = 1; end 83

84 Repetitive Signals (clock) Test Bench - Generating Clock Clock A Simple Solution: wire Clock; assign #10 Clock = ~ Clock Caution: Initial value of Clock (wire data type) = z ~z = x and ~x = x 84

85 Test Bench - Generating Clock (cont.) Initialize the Clock signal initial begin Clock = 0; end Caution: Clock is of data type wire, cannot be used in an initial statement Solution: reg Clock; initial begin Clock = 0; end always begin #10 Clock = ~ Clock; end forever loop can also be used to generate clock 85